Alphawave Semi has announced the successful tape-out of its UCIe 3D IP on TSMC’s SoIC-X advanced packaging technology, part of the 3DFabric platform. The company reports that this integration delivers a tenfold improvement in power efficiency and up to five times greater signal density compared to traditional 2.5D die-to-die interfaces. The solution targets high-performance applications in data centers, artificial intelligence (AI), and high-performance computing (HPC).
The UCIe (Universal Chiplet Interconnect Express) 3D IP supports face-to-face die configurations, enhancing chiplet integration by enabling more efficient communication between stacked dies. Alphawave Semi notes that its 5 nanometer (nm) bottom die supports through-silicon vias (TSVs) to provide power and ground to the 3 nm top die. Additionally, the company offers a proprietary design flow and methodology to accelerate the construction and verification of 3D device stacks.
As data center and AI workloads scale, Alphawave Semi reports that conventional planar designs are constrained by edge space for inter-die communication. By utilizing 3D die stacking, designers can increase bandwidth density and power efficiency, moving beyond monolithic system-on-chip (SoC) architectures toward disaggregated chiplet-based solutions.
This milestone builds on Alphawave Semi’s June 2023 announcement of its UCIe IP tape-out on TSMC’s 2 nm process using 2.5D CoWoS technology. The company is also pursuing next-generation UCIe solutions featuring 64 gigabits-per-second (Gbps) support aimed at advancing chiplet-based systems for AI and HPC.
Mohit Gupta, Executive Vice President and General Manager at Alphawave Semi, said, “This successful tape-out represents a significant milestone for Alphawave Semi and our AI platform,” immediately highlighting that the company is “directly addressing the memory and bandwidth bottlenecks that limit our customers’ next-generation AI and HPC applications.” Gupta adds, “This is a testament to our team’s innovation and our commitment to enabling a new class of chiplet-based systems.”
Juan C. Rey, Senior Vice President and General Manager of the Calibre product line at Siemens Digital Industries Software, stated, “Siemens is pleased to partner with Alphawave Semi to offer both their industry leading 3DIO IP and Siemens’ advanced 3D IC design and verification platforms,” noting the companies are “enabling early-stage analysis of critical electrical and thermal parameters that drive the performance, efficiency, and reliability of next-generation 3D IC systems.”
Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC, commented, “The partnership we have with our Open Innovation Platform design ecosystem partners like Alphawave Semi is essential for enabling our mutual customers to fully harness TSMC’s industry-leading 3DFabric advanced packaging and 3D stacking technologies in their designs,” stating that the latest collaboration “is a prime example of our drive to enable energy efficiency and higher performance in AI systems, helping our customers push the envelope of product innovation.”
Source: Alphawave Semi
