Alphawave Semi has announced the successful tapeout of its third-generation UCIe (Universal Chiplet Interconnect Express) die-to-die intellectual property (IP) subsystem on TSMC’s 3 nanometer (nm) process technology. This subsystem achieves 64 Gbps per-lane uni-directional data rates, doubling the shoreline bandwidth density over previous generations. Alphawave Semi claims this advancement enables more scalable XPU and data center chiplet architectures, allowing for power-efficient, high-reliability system-on-chip (SoC) integration and supporting seamless interoperability across chiplet-based designs.
This Gen3 subsystem is the first 64 Gbps UCIe IP subsystem implemented on TSMC’s 3 nm process, according to Alphawave Semi. Targeting hyperscale and data center environments, the technology aims to deliver robust die-to-die connectivity for high lane-count architectures such as artificial intelligence (AI) acceleration and next-generation cloud infrastructure. The subsystem supports optical connectivity for Co-Packaged Optics (CPO), a requirement for scalable, high-radix systems. Alphawave Semi also notes the subsystem supports custom memory interfaces designed for very low-power and low-latency operation, offering eight times the bandwidth density of conventional memory standards.
Alphawave Semi reports the Gen3 UCIe subsystem achieves up to 3.6 Tbps per millimeter shoreline bandwidth in standard packages and over 21 Tbps per millimeter in advanced packaging. The silicon-proven architecture spans multiple process nodes, and the subsystem incorporates adaptable firmware for rapid deployment of chiplet-based solutions. Integration features include support for protocols such as AXI-4, AXI-S, CXS, CHI, and CHI C2C, enabling flexible design and reference architectures for accelerated development cycles.
Compliance with UCIe 3.0—released in August 2025—is highlighted, along with test and debug capabilities such as iJTAG, built-in self-test (BIST), design-for-test (DFT), Known Good Die (KGD) checks, and live per-lane health monitoring. These features are designed to ease integration and improve reliability for hyperscale and data center applications.
Mohit Gupta, Executive Vice President and General Manager at Alphawave Semi, stated, “The industry’s first tapeout of our Gen3 UCIe IP at 64 Gbps on TSMC’s N3P process marks a significant leap forward in die-to-die connectivity,” and continued, “Building on our success on the silicon for 36 Gbps UCIe IP at N3P, this achievement positions Alphawave Semi at the forefront of delivering ultra-high-performance and shoreline bandwidth density compared to prior generations. Just as importantly, it strengthens our broader AI platform—ensuring our suite of IP subsystems now delivers higher performance and efficiency than ever before on the 3nm process to meet the critical bandwidth demands of scalable AI compute.”
Aveek Sarkar, Director of Ecosystem and Alliance Management Division at TSMC, commented, “Our collaboration with Alphawave Semi reflects our shared commitment to advancing high-performance, energy-efficient computing through leading design solutions on TSMC’s 3nm technology,” with the additional statement, “This achievement demonstrates how close collaboration with our Open Innovation Platform partners accelerates the delivery of advanced interface IP and custom silicon solutions to meet the rapidly growing demands of AI and cloud infrastructure.”
Source: Alphawave Semi
