MIPS, a GlobalFoundries company, has announced that its I8500 processor is now sampling to lead customers. The announcement was made at the GlobalFoundries Technology Summit in Munich, Germany. The I8500 is positioned as an intelligent data movement processor intellectual property (IP) for real-time, event-driven platforms. According to MIPS, this design targets hyperscale operators, storage, data center networks, automotive, industrial, and communications infrastructure use cases, supporting high-performance and deterministic data orchestration for the era of Physical AI and the growing demand for edge AI computing.
The MIPS I8500 features a scalable multithreaded architecture, supporting four threads per core and deployment in multi-cluster configurations—allowing up to 24 threads per cluster. The processor, built using the open RISC-V instruction set architecture (ISA), delivers low-latency, deterministic data movement with integrated security features. MIPS says these capabilities are well suited for orchestrating packet flows across accelerators and enabling intelligent communication between compute hardware, operators, and networks in real time. The I8500 also supports RVA23 profile readiness along with Linux and real-time operating systems, enabling software portability and alignment with existing ecosystems. The design emphasizes energy efficiency for edge workloads.
MIPS lists the following data center and industrial applications for the I8500: high-speed rule-based packet classification for Smart Network Interface Cards (NICs), Data Processing Units (DPUs), and backhaul processors; real-time protocol and routing for industrial Internet of Things (IoT) workloads; deterministic, secure data management for predictive maintenance and AI-driven diagnostics; and support for scalable deployments in 5G, 6G, and edge computing environments using multi-core, multi-cluster configurations. Additional features include dynamic traffic management, encryption, and quality of service (QoS) with programmable pipelines for secure, high-performance communication channels.
MIPS notes that the I8500 Atlas Explorer Core Model is now available for evaluation, enabling co-design with software and hardware to accelerate prototyping and optimize time to deployment cycles.
“The MIPS I8500 is a timely and strategic advancement for embedded and edge computing,” said Steven Dickens, CEO and Founder at HyperFRAME Research. “The combination of scalable multithreading, deterministic performance, and secure data orchestration directly addresses the growing demand for real-time, event-driven processing in markets like automotive, industrial automation, and communications infrastructure. MIPS is clearly positioning itself as a leader in enabling Physical AI at the silicon level.”
Source: MIPS
