According to Chelsio, the T7 DPU provides full hardware offload for NVMe over TCP, NVMe over Fabrics (NVMe-oF) with iWARP and RoCEv2, User Datagram Protocol (UDP), and iSCSI, supporting ultra-low-latency Just-a-Bunch-of-Flash (JBOF) and all-flash storage deployments. The platform includes in-line security features—such as IPsec, Transport Layer Security (TLS), kernel TLS (kTLS), traffic filtering, and advanced packet classification—to protect data in motion. Hardware-based end-to-end data integrity is also supported.
Additional technical features include a Controller Memory Buffer (CMB), advanced NVMe support for latency-sensitive workloads, and built-in hardware engines for compression, deduplication, RSA encryption, RAID 5/6, erasure coding, Persistent Memory over Fabrics (PMoF), and QUIC protocol acceleration. The DPU features integrated PCI Express (PCIe) switch functionality for adapter or host mode, a native Field-Programmable Gate Array (FPGA) integration interface for customized acceleration, and a flexible architecture for hosting multiple adapters or acting as a hosted endpoint via upstream CPUs.
Chelsio is offering the T7 platform in two variants: the T7, targeting high-end storage appliances, security platforms, and AI networking; and the S7, a cost-optimized, DRAM-less version for high-volume cloud and server deployments. The company reports that T7 silicon maintains software compatibility with previous generations (T4, T5, and T6), allowing seamless migration to faster Ethernet and PCIe speeds.
In an industry analyst brief, Brandon Hoff, Executive Analyst at IDC, commented, “DPUs offer a compelling solution for organizations looking to support AI and storage workloads on Ethernet,” said Brandon Hoff, Executive Analyst at IDC. “The Chelsio T7 DPU offers high-performance offloads and congestion control based on open standards; capabilities that make it a flexible and scalable option for modern infrastructure needs from a company with a strong track record.”
Chelsio notes it will demonstrate the T7 architecture and its key capabilities for high-performance storage, security, and AI networking at the Future of Memory and Storage (FMS) 2025, scheduled for August 5 to 7 in Santa Clara, California.
Source: Chelsio Communications













