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XCENA launches MX1 CXL memory expansion to scale AI inference KV cache

XCENA introduced its MX1 production memory lineup, a CXL-based platform the company is aiming at AI inference infrastructure where memory capacity, utilization, and data movement can limit scaling.

MX1 is designed to work with Intel Xeon 6 platforms, using Compute Express Link (CXL) to expand or pool memory for memory-intensive AI workloads, including growing KV cache footprints tied to larger models and longer context windows.

MX1 follows the earlier MX1P prototype platform, which XCENA says is currently deployed in proof-of-concept engagements and technical collaborations globally with customers. With MX1 moving into a production lineup, XCENA says it intends to advance those engagements toward production-level evaluation and commercialization discussions with hyperscalers, cloud service providers, and enterprise AI infrastructure customers.

MX1 product lineup

The MX1 lineup includes two products: MX1 Compute and MX1 Expand.

MX1 Compute pairs CXL-based memory expansion with near-data processing enabled by 2,048 RISC-V cores. The design places compute adjacent to memory so data-intensive operations can run where data resides, targeting reduced CPU-to-memory data movement and improved system efficiency.

MX1 Expand provides eight DRAM slots and is aimed at DRAM reuse and server scale-up, positioning it as a way to expand memory resources across AI infrastructure.

Demonstrations and engineering takeaways

At FMS 2026, XCENA is demonstrating a CXL memory pool of up to 20 TB using memory pooling systems, along with a KV cache sharing demo intended to show more efficient use of shared memory resources for AI inference infrastructure. It’s a practical focus: for inference, KV cache growth can turn memory into the gating resource long before compute is fully utilized, so anything that improves memory scaling and utilization can directly affect how many concurrent requests a cluster can sustain.

XCENA is also demonstrating a CXL-based memory architecture on Intel Xeon 6, including KV cache offload to CXL-attached memory to improve memory scalability and utilization efficiency for AI servers.

“AI performance is no longer limited by compute, it’s limited by memory, and MX1 is our answer,” said Jin Kim, CEO of XCENA.

“As AI inference scales, efficiently expanding and utilizing memory is becoming increasingly important for hyperscale infrastructure,” said Debendra Das Sharma, Senior Fellow and Chief I/O Architect at Intel.

Source: XCENA

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