Microchip ships PCIe 6.0 and CXL 3.1 retimers with sub-12 ns latency

Microchip Technology has released XpressConnect PCIe 6.0 and CXL 3.1 retimers aimed at signal-reach, latency, and signal-integrity limits that show up as AI fabrics push to 64 GT/s. For data center architects building large GPU clusters, the company is pitching the parts as enablers for memory expansion and resource disaggregation when electrical budgets and board-level routing make it hard to scale links cleanly at Gen 6 speeds.

The retimers are designed to extend signal reach beyond conventional PCIe Gen 5 and Gen 6 electrical limits, which can matter in systems that mix long baseboard routes, riser cards, and cabled interconnects. Microchip also calls out support for “stringent thermal and power budgets” in modern AI fabrics, tying the devices to real-world constraints in high-density GPU servers where every watt of interconnect overhead competes with accelerator power and cooling headroom.

On latency, Microchip specifies pin-to-pin latency of less than 12 ns, which it describes as approximately 80% lower than PCIe 6.0 specifications. In dense GPU clusters, retimer latency isn’t just a link-detail; it can stack up across topologies and contribute to stalls, so the pin-to-pin number is one of the few retimer specs that’s immediately useful when you’re trying to model end-to-end behavior and decide how aggressively to extend reach.

XpressConnect retimers are also positioned as part of a broader Microchip data center stack. Microchip says the retimers are engineered to work alongside its 3-nm Switchtec PCIe Gen 6 switches, Adaptec SmartRAID controllers and host bus adapters, and Flashtec NVMe controllers to help enable what it describes as a pre-validated, interoperable fabric. The retimers can integrate with PCIe Gen 3, Gen 4, and Gen 5 platforms “where required,” which Microchip says can reduce time to market.

For bring-up and operations, the retimers connect into Microchip’s ChipLink diagnostic ecosystem, which includes a unified GUI for real-time 2D eye capture and four-level pulse amplitude modulation (PAM4) telemetry. Microchip says ChipLink connects via in-band PCIe or sideband interfaces including UART, TWI, and EJTAG, supporting debug, diagnostics, configuration, and analysis.

Microchip says the devices support link bifurcation configurations of 1×16, 2×8, and 4×4, align with widely adopted retimer footprint guidelines, and include hot-plug support and end-to-end data integrity features. The company also describes XpressConnect as an “industry-standard, drop-in solution” intended to help hyperscalers reduce the risk of single-vendor dependency.

“As PCIe 6.0 pushes speeds to 64 GT/s, signal reach and latency become critical design challenges,” said Brian McCarson, corporate vice president and GM of Microchip’s data center solutions business unit.

Microchip says XpressConnect PCIe Gen 6 and CXL 3.1 retimers can be purchased directly from the company or through authorized distributors. The product line sits under Microchip.