Astera Labs has expanded its Leo Smart Memory Controller family with three new devices aimed at agentic AI and general-purpose cloud infrastructure: Leo X-Series, plus Leo 2 E-Series and Leo 2 P-Series. The additions span two architectures data center operators are actively evaluating for memory-constrained AI stacks—fabric-attached memory on the accelerator side and CXL-based memory expansion, pooling, and sharing on the CPU/host side.
The new Leo X-Series is a fabric-attached Smart Memory Controller intended to connect a dedicated memory tier directly to AI fabrics for offloading KV cache and agent context. Astera Labs pairs it with Scorpio fabric switches, using PCIe and platform-specific protocols for GPU scale-up fabrics. For long-context inference workloads where KV cache size can cap concurrency and inflate response times, a direct path to a memory tier is the architectural point—and Astera Labs reports up to 62% faster time to first token (TTFT) and up to 22% more tokens per second (TPS) in its internal testing.
Those performance numbers are worth treating as workload- and platform-dependent, but the direction is clear: moving KV cache off CPU-attached DRAM or lower tiers like storage is one of the few levers operators have when model context windows and multi-turn sessions keep growing faster than practical DRAM per node.
On the CXL side, Astera Labs introduced the Leo 2 E-Series and Leo 2 P-Series for CPU-attached memory expansion and rack-scale memory utilization. Both support four DDR4 or DDR5 memory controllers, which Astera Labs says doubles memory bandwidth and capacity versus the previous generation, and the company notes an optimized package intended to fit add-in cards and other dense DIMM-integration designs.
Leo 2 E-Series targets direct CPU-attached CXL 3.2 memory expansion via PCIe 6 with x16 host connectivity. Leo 2 P-Series targets disaggregated CXL memory architectures, supporting pooling and sharing across hosts via dual-port PCIe 6 x8 connectivity and dynamic capacity management.
A blunt takeaway: PCIe 6 and CXL 3.2 put serious signaling and integration demands on the platform, but they also align with where operators want memory to go—more composable, more reusable, and less stranded per server.
Across the Leo family, Astera Labs is emphasizing hyperscale-grade RAS features, memory-health management, on-chip hardware engines, and automated repair, including support for reusing previously deployed DDR4 DIMMs alongside DDR5 in new server fleets. The company also points to telemetry and management integration via its COSMOS software suite for fleet-wide visibility across mixed-memory deployments.
“Agentic AI is where the economics of AI infrastructure are being decided, and those economics depend on putting every usable gigabyte of memory to work,” said Thad Omura, senior vice president, Compute Connectivity Group at Astera Labs.
Astera Labs said the enhanced Leo family was developed in collaboration with ecosystem partners including AMD, Arm, Intel, and major memory suppliers, and that the products are sampling with hyperscaler customers.
Source: Astera Labs
