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CXL-connected MRAM demo adds persistent memory tier with 100x NAND writes

Everspin Technologies demonstrated a CXL-connected MRAM platform at SNIA Developer Conference (SDC) 2026, aiming to add a persistent memory tier between DRAM and NAND-based storage for memory-semantic access. The company describes the platform as “the world’s first” CXL-connected MRAM implementation and says it’s ready for customer workload testing.

The working system connects Everspin PERSYST MRAM to CXL-enabled platforms as persistent memory with memory semantics, pairing CXL’s connectivity with MRAM’s ability to retain data without power. Everspin says the platform is intended to act as a persistent buffer and cache tier with cache-line-level, nanosecond-class access and writes up to 100x faster than NAND-based solid-state storage. The company also says data remains available through a power interruption or system restart without relying on battery-backed DRAM or flushing data to an SSD.

The demo configuration uses a Supermicro AS-1116CS-TN server with an AMD EPYC 9355 32-core processor, plus an AMD Alveo U250 FPGA platform with a Wolley CXL controller and Everspin PERSYST 1 GB DDR4 MRAM UDIMMs. Everspin characterized the setup as an open, standards-based platform for demonstrating coherent access to persistent MRAM through CXL.

For data center architects, the interesting technical angle is the combination of coherency and persistence. If MRAM can be exposed reliably as CXL-attached persistent memory, it opens up an additional design point for fast commit, write buffering, and persistent caches without the operational trade-offs that come with battery-backed DRAM—and with a different latency and endurance profile than NAND SSDs. But performance claims like “up to 100x faster writes than NAND” will hinge heavily on access patterns, queue depths, and how the CXL path and controller behave under real application pressure.

“We now have a working system so customers can run their own workloads and measure the benefit for their specific applications,” said Sanjeev Aggarwal, president and CEO of Everspin Technologies. Wolley CEO Dr. Bernard Shung said, “Together, we are demonstrating a practical way to connect persistent memory through CXL and make it available to today’s compute platforms.” Everspin said the platform creates opportunities in AI systems for applications such as checkpointing and persistent key-value (KV) cache.

Source: Everspin Technologies

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