Navitas Semiconductor has launched two new SiC MOSFET package options for its 5th generation GeneSiC technology platform: a top-side cooled QDPAK surface-mount package and a low-profile TO-247-4-LP through-hole package with asymmetrical leads. The company says the new 1200 V GeneSiC MOSFETs target higher power density and ruggedness, with packaging aimed at tighter thermal and mechanical constraints in systems like AI data center power supplies.
Navitas’ 5th generation Trench-Assisted Planar (TAP) technology is described as delivering a 35% improvement in the RDS,ON × QGD figure of merit and about a 25% improvement in the QGD/QGS ratio. Navitas also highlights a stable high threshold voltage, VGS,TH, of >3 V, which it says “ensures immunity against parasitic turn-on,” with “predictable switching performance.”
The top-side cooled QDPAK is positioned as a response to “thermal limitations of conventional PCB cooling,” moving the primary heat path through the top of the package to a heatsink. Navitas claims the approach improves heat dissipation efficiency, supports smaller system footprints, and reduces parasitic inductance for cleaner switching at high frequency. For mechanical and insulation-related details, Navitas specifies a 15 mm x 21 mm footprint and 2.3 mm height, creepage extended to 5 mm via a groove in the mold compound, and support for up to 1000 VRMS applications using an epoxy molding compound with CTI >600.
The low-profile TO-247-4-LP variant is aimed at designs where vertical clearance is constrained, which Navitas explicitly ties to “high-density AI power racks.” The company says reducing package height on the PCBA enables higher power density versus a standard TO-247-4, and that asymmetrical leads (thin leads for gate and Kelvin-source) are intended to improve PCBA manufacturing tolerances.
Navitas listed four initial 1200 V parts across the two packages: G5R06MT12QP (QDPAK, 6.5 mΩ), G5R12MT12QP (QDPAK, 12 mΩ), G5R06MT12LK (TO-247-4-LP, 6.5 mΩ), and G5R12MT12LK (TO-247-4-LP, 12 mΩ.
“The introduction of top-side cooled QDPAK, and low-profile TO-247-4-LP packages is a direct response to the need for ‘more power in less space’,” said Paul Wheeler, VP & GM of the SiC business unit at Navitas.
Navitas also said a white paper on its 5th generation TAP technology is available as a free download on its website, and that sample requests can be made through a Navitas representative or via info@navitassemi.com. Navitas uses the term “AEC-Plus” to indicate parts exceeding AEC-Q101 and JEDEC reliability testing standards, based on Navitas test results.
Source: Navitas
