Panmnesia introduces PCIe 6.0 and CXL 3.2 fabric switch for data centers

Panmnesia has announced sample availability of its PCI Express (PCIe) 6.0 and Compute Express Link (CXL) 3.2 Fabric Switch, which it says is the first CXL switch silicon to support port-based routing. According to Panmnesia, the silicon operates as a hybrid solution supporting both PCIe Gen 6 and CXL 3.2 protocols on a single chip, maintaining full backward compatibility with all previous PCIe and CXL generations. The switch implements both port-based and hierarchy-based routing modes as described in the CXL 3.2 and PCIe 6.0 specifications.

The Fabric Switch uses Panmnesia’s proprietary PCIe and CXL controller and features a full-stack optimized architecture. It is designed for data center operators seeking composable infrastructure with reduced capital and operating expenditures, and is aimed at supporting high-performance, large-scale, multi-device workloads. Explicitly targeted use cases listed by Panmnesia include artificial intelligence (AI) training—such as Deep Learning Recommendation Models (DLRM), large language models (LLMs), and retrieval augmented generation (RAG)—and high performance computing (HPC) workloads that use message passing interface (MPI) for scientific simulations.

For technical detail, Panmnesia notes that the switch supports self-organizing, topology-agnostic fabrics using port-based routing, enabling AI clusters to operate as a unified accelerator. The switch can connect thousands of devices across racks through cascading, reducing network latency. It delivers PCIe Gen 6 data rates of 64 gigatransfers per second (GT/s), supports all CXL subprotocols—including CXL.cache, CXL.mem, and CXL.io—for cache coherency and data sharing, and achieves double-digit nanosecond internal latency through a high-fan-out design and proprietary controller integration.

Panmnesia confirms that the switch silicon is now available for early access partners. The embedded PCIe 6.0 and CXL 3.2 controllers are silicon-proven, and variants for memory, accelerator, and CPU interfaces can be requested as standalone products.

Source: Panmnesia

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