Cadence and TSMC expanded their collaboration to support design and signoff for next-generation AI silicon on TSMC’s advanced process technologies, including N3, N2, A16, and A14. The work spans Cadence IP, end-to-end design infrastructure, and certified flows intended to improve correlation and reduce design iterations for DTCO-focused AI and HPC chips.
The expanded scope covers “signoff-ready” flows that scale from SoCs to chiplet and 3D-IC architectures, with a focus on tapeout-quality convergence on TSMC’s latest nodes. Cadence said it is delivering IP for TSMC N2P, including DDR5 12.8G MRDIMM, PCIe 6.0, LPDDR6/5X 14.4G, and HBM4E 16G, and that its Artisan foundation IP portfolio is now in production designs on TSMC N3.
On the EDA side, Cadence listed certified support for TSMC N2 and A16 across multiple tools: Innovus Implementation System; Virtuoso Studio and the Spectre Simulation Platform; Celsius Thermal Solver, Voltus IC Power Integrity Solution, and EMX Planar 3D Solver; and signoff tools including Tempus Timing and ECO Solution, Quantus Extraction Solution, Liberate Characterization Portfolio, and Pegasus Verification System. Cadence also said Genus Synthesis Solution is enabled for these process technologies, with ongoing collaboration on Clarity 3D Solver, and that it is working with TSMC on A14 PDKs to accelerate convergence for AI and HPC designs.
For 3D-IC and heterogeneous integration, Cadence said the Integrity 3D-IC Platform supports the TSMC-COUPE Reference Flow for stacked-die, while Virtuoso Studio adds silicon photonics support through its heterogeneous integration methodology. Cadence also described a Celsius thermal-aware flow that includes PIC placement with Virtuoso and signal integrity analysis with EMX, along with quality checks and physical verification using Pegasus.
Alongside the flow and IP work, Cadence said it is preparing “agent-ready” design flows, optimization engines, and signoff infrastructure with TSMC, tying into its “agentic AI” effort to shift EDA toward goal-driven execution. That matters because on leading-edge nodes, small mismatches between pre-route expectations and post-route reality can turn into extra spins, schedule slip, and painful power and thermal surprises.
Cadence also described optimization for TSMC NanoFlex Pro standard cell architecture using Genus, Innovus, and Cadence Cerebrus Intelligent Chip Explorer, aimed at DTCO and finer tuning of speed and power efficiency during floorplan and placement. The company said improved front-end placement and back-end routing rules are intended to improve pre-route and post-route correlation, and noted TSMC’s A16 Super Power Rail approach of routing power nets on the backside of the chip to support denser and faster designs. In custom design, Cadence said agentic AI is embedded in Virtuoso Studio flows, including enablement for an N2-to-A14 Analog Design Migration flow.
Chin-Chi Teng, senior vice president and general manager at Cadence, said, “AI silicon innovation at advanced nodes demands a signoff-ready approach that spans the full design cycle and scales from SoCs to chiplet and 3D-IC architectures.”
TSMC’s Aveek Sarkar, Director of the Ecosystem and Alliance Management Division, said the collaboration aims to help customers design on TSMC’s latest process technologies and 3DFabric advanced packaging solutions.
Positron CTO Thomas Sohmers said Positron is licensing Cadence’s PCIe 6.0 SerDes IP on the TSMC N3P node for an AI inference accelerator optimized for transformer workloads, and cited Cadence’s Genus and Innovus tools as part of its path to tapeout.
Source: Cadence
