Cerebras has introduced the CS-4, a rack-scale AI accelerator built from three Wafer Scale Engine 3 Turbo (WSE-3T) processors. The company is pitching the system around inference performance and efficiency, including claims of up to 30x higher tokens-per-second-per-user versus GPU-based solutions and up to 10x more throughput per watt than its prior CS-3 system.
At the rack level, CS-4 is specified at 750 PFLOPs of AI compute, 7.2 Tbit/s of I/O, and 129.6 PByte/s of memory bandwidth. Cerebras also lists total compute fabric bandwidth at 160.5 PByte/s and wafer-to-wafer latency as low as 2 microseconds, positioning the platform for large clusters and models with more than 50 trillion parameters.
For data center operators, the headline numbers matter less than the architecture choices behind them: bandwidth, latency, and power delivery are usually what set the ceiling for real inference throughput once a system is deployed at scale. But the performance comparisons here are still vendor-provided, and the practical question will be how these claims hold up across model types, context lengths, and serving configurations.
CS-4 is the first system in what Cerebras calls its Nexus platform architecture, organized around modular “Compute, Power and I/O” building blocks. A key mechanical change is a rear-mounted, vertically attached “backpack” compute subsystem. Cerebras says the Wafer-Scale Backpack integrates power conversion, direct liquid cooling, high-speed I/O, and control electronics around the wafer, cuts deployment time from days to hours versus the prior generation, reduces component count by 50%, and uses 60% more automated manufacturing.
On the power side, Cerebras says Nexus moves power conversion much closer to the processors—citing a shift from roughly 50 millimeters on conventional GPU boards to approximately 0.5 millimeters—aimed at reducing board-level losses. The company ties that to “twice as much power” delivered to the WSE-3T, enabling higher operating frequencies.
Networking and integration hinge on a new programmable Wafer I/O Module. Cerebras says it supports RoCE v2 RDMA over Ethernet and doubles aggregate off-wafer bandwidth to 2.4 Tbit/s per wafer (7.2 Tbit/s per CS-4). It also supports “Direct Wafer Links,” a switchless mode intended to link wafers within and across racks with wafer-to-wafer latency as low as 2 microseconds. Cerebras also points to disaggregated inference flows where a separate “prefill engine” hands off to Cerebras for low-latency decode, naming AMD Helios and AWS Trainium as examples of ecosystem partners.
At the processor level, WSE-3T is specified at four trillion transistors, 900,000 AI-optimized cores, 46,225 mm² of silicon, and 44 GB of on-wafer SRAM. Cerebras says WSE-3T doubles per-wafer AI compute to 250 PFLOPs and doubles memory bandwidth to 43.2 PByte/s, with on-chip fabric bandwidth and off-chip I/O both doubled to 53.5 PByte/s and 2.4 Tbit/s, respectively. I/O latency is listed as shrinking from 5 microseconds to as low as 2 microseconds.
In a Cerebras-provided comparison on GPT-OSS-120B with “identical prompts,” the company says CS-4 delivers more than 4,400 tokens per second per user, and notes that actual throughput varies by model architecture, context length, precision, and serving configuration.
Cerebras said first CS-4 shipments begin this quarter, and the company has posted a CS-4 datasheet at cerebras.ai/cs4-datasheet.
Source: Cerebras
