JEDEC Solid State Technology Association has announced it is nearing completion of a new standard for Standard Package High Bandwidth Memory (SPHBM4). According to JEDEC, SPHBM4 devices utilize the same memory die technology as High Bandwidth Memory 4 (HBM4) but are designed for mounting on standard organic substrates, as opposed to the silicon substrates required by HBM4. This new packaging approach is specifically relevant for data center deployment and artificial intelligence accelerators, where both substrate considerations and memory bandwidth are critical.
JEDEC reports that SPHBM4 maintains the aggregate data throughput of HBM4 but achieves this using fewer pins and higher frequency operation. While the HBM4 interface uses 2048 data signals, the SPHBM4 specification—when published—will define an interface with 512 data signals and employ 4:1 serialization to match bandwidth performance. This pin reduction supports the relaxed bump pitch necessary for organic substrate compatibility.
JEDEC states that SPHBM4 retains identical memory capacity per stack as HBM4 due to the use of the same memory core layers. An additional capability enabled by organic substrate routing is support for longer channel lengths between the system-on-chip (SoC) and memory. This, according to JEDEC, can allow for a higher total number of SPHBM stacks within a system, potentially increasing overall system memory capacity—an important factor for servers and accelerators within modern data centers.
“JEDEC members are actively shaping the standards that will define next generation modules for use in AI data centers, driving the future of innovation in infrastructure and performance,” said Mian Quddus, Chairman of the JEDEC Board of Directors.
JEDEC notes that its standards are subject to change during and after the development process, including potential disapproval by the JEDEC Board of Directors.
Source: JEDEC
