DDR5 9600 RDIMM chipset hits 9600 MT/s with Rambus RCD06 and PMIC5030

Rambus has introduced a DDR5 9600 Server RDIMM chipset aimed at next-generation CPU-based servers running AI, HPC, and other data-intensive workloads. The company’s pitch is straightforward: faster RDIMMs and tighter power management as memory bandwidth and capacity pressure climbs alongside large-scale inference and “agentic” workflows.

The centerpiece is Rambus’ 6th Generation Registering Clock Driver, the RCD06, specified to operate at up to 9600 MT/s. Rambus puts that at a 20% data-rate increase over its prior generation solution. The chipset is designed to enable RDIMMs operating at up to 9600 MT/s.

Beyond the registering clock driver, the DDR5 9600 RDIMM chipset is positioned as a full RDIMM support stack for module builders. It includes the PMIC5030 power management IC, an SPD Hub with an integrated temperature sensor, and dedicated Temperature Sensor ICs. Rambus frames the bundle as a way to simplify module development and shorten time to market by pulling clocking, control, telemetry, and power management into one cohesive chipset.

On the engineering side, this type of integration matters most when you’re pushing data rates and loading up channels: signal integrity, power integrity, and thermal monitoring stop being “nice to have” and become the difference between a module that can pass validation at speed and one that can’t. The more CPU platforms scale core counts and memory channel density, the less tolerance there is for weak margins in RDIMM clocking and power delivery.

Rambus ties the need for higher bandwidth and capacity to iterative, memory-heavy AI workloads, and specifically calls out key-value (KV) caching in large language model inference as a driver for additional memory capacity and bandwidth demand. In that context, a 9600 MT/s RDIMM-capable chipset is a clear attempt to keep CPU-based platforms fed as workloads shift toward sustained inference and orchestration patterns that can be memory-bound.

“The rapidly accelerating adoption of agentic AI and AI inference workloads is driving unprecedented demand for higher memory bandwidth and capacity in the data center,” said Rami Sethi, SVP and general manager of Memory Interface Chips at Rambus.

IDC associate VP Soo Kyoum Kim added: “As data center architectures evolve to support increasingly complex workloads, memory bandwidth, latency and reliability are becoming critical system-level design considerations.”

More details on the product are available on the Rambus DDR5 DIMM chipset page.