Rambus has introduced a power management IC (PMIC) designed for LPDDR6 Small Outline Compression Attached Memory Modules (SOCAMM2), targeting low-power, high-performance server memory modules for accelerated AI infrastructure. The LPDDR6 SOCAMM2 standard is still in development, and Rambus says the new PMIC is aimed at supporting that next step in LPDDR-based server memory.
The PMIC is part of Rambus’ LPDDR-based server module solution set, and it’s positioned to help operators push more AI throughput within fixed power budgets, often discussed in terms of tokens per watt. Rambus says it developed the device in technical cooperation with customers and ecosystem partners.
At a module level, Rambus describes the LPDDR6 SOCAMM2 PMIC and a companion SPD Hub as handling power conversion, sequencing, telemetry, and fault protection. In practical terms, that’s the plumbing required to make a serviceable, modular LPDDR-based memory approach workable in server platforms where power integrity, orderly bring-up, and visibility into module behavior are non-negotiable.
Rambus also outlined its broader server-memory power management portfolio, which includes registering clock drivers (RCDs), PMICs, voltage regulators, SPD Hubs, and temperature sensors for DDR- and LPDDR-based modules. The company already offers a complete LPDDR5X SOCAMM2 chipset for current-generation SOCAMM2 modules, and it says the new LPDDR6 SOCAMM2 PMIC, together with the Rambus SPD Hub, extends that roadmap to the upcoming LPDDR6 generation.
One blunt takeaway for data center engineers: a PMIC “designed for LPDDR6 SOCAMM2” is an enablement step, not a signal that LPDDR6 SOCAMM2 modules are ready to deploy broadly. But power delivery, sequencing, and protections are exactly where early module ecosystems tend to stumble, so getting that layer defined early matters.
“Our new PMIC designed for LPDDR6 SOCAMM2 builds on our leadership in server-memory power management,” said Rami Sethi, senior vice president and general manager of Memory Interface Chips at Rambus. “Working closely with industry leaders in alignment with the broader AI ecosystem, we are helping enable the high-performance, power-efficient memory architectures that maximize tokens per watt for AI workloads.”
Micron also pointed to the role of low-power DRAM in emerging AI platforms. “As AI systems place growing demands on memory capacity, bandwidth and power efficiency, LPDRAM is becoming an increasingly important technology for next-generation AI infrastructure,” said Praveen Vaidyanathan, vice president and general manager of Cloud Memory Products at Micron Technology.
Rambus says the LPDDR6 SOCAMM2 PMIC is currently sampling to lead customers. For more details on the platform, Rambus points to its SOCAMM2 server module chipset page.
Source: Rambus
